module BranchLogic(icode, ifun, CC, Bch);
input [3:0] icode;
input [3:0] ifun;
input [31:0] CC;

output reg Bch;

always @(*) begin
	if(icode == 7) begin
		case(ifun)
			0: begin
				Bch <= 1;
			end
			1: begin
				Bch <= (CC[31] ^ CC[29]) | CC[30];
			end
			2: begin
				Bch <= (CC[31] ^ CC[29]);
			end
			3: begin
				Bch <= CC[30];
			end
			4: begin
				Bch <= ~CC[30];
			end
			5: begin
				Bch <= ~(CC[31] ^ CC[29]);
			end
			6: begin
				Bch <= ~(CC[31] ^ CC[29]) & ~CC[30];
			end
			default: begin
				Bch <= 0;
			end
		endcase
	end else begin
		Bch <= 0;
	end
end

endmodule
